The present invention relates to a semiconductor device and a manufacturing method thereof, in particular, comprising a self align contact hole.
The integration degree of a semiconductor device is mainly improved by the progress of the fine processing technology and also depends on the advancement of the multilayer wiring technology. From a viewpoint of the improvement of the integration degree, one of the important technical issues in the multilayer wiring technology is how to connect an upper wiring layer directly to a lower wiring layer avoiding a connection via a middle wiring layer. As a typical example of a solution of such a technical issue, a self align contact hole is now being watched. The self align contact hole reaching from the upper wiring layer to the lower wiring layer is provided at the middle wiring layer as a self matching i.e. at a vacant part of the middle wiring layer, at a lower part than an upper surface of the middle wiring layer. At a part of the self align contact hole, an insulation separation between the third wiring layer (and the first wiring layer) and the second wiring layer is implemented by an insulation film spacer provided at a side of the self align contact hole.
The self align contact hole is adopted in a normal multilayer wiring and is also becoming larger usage in DRAM corresponding to the reduction of the size of memory cell. In particular, at the COB (Capacitor Over Bit-line) structure DRAM provided a storage node electrode at the upper layer of the bit-line, a tendency to use a self align contact hole for a bit contact hole and a node contact hole is getting larger, wherein a bit contact hole is a hole to connect a bit line to one side of a source drain area and a node contact hole is a hole to connect a storage node electrode that is a lower electrode of capacitor to the other side of a source drain area. In this case, the bit contact hole is self matching to a gate electrode which also serves as a word line, the node contact hole is self matching to both a gate electrode and a bit line. Next, the conventional self align contact hole is explained, with an example which the bit contact hole and the node contact hole of the COB structure DRAM are made of the self align contact holes.
Referring to FIG. 1 showing a plan view of DRAM, FIGS. 2A and 2B showing section views of DRAM and section views of both Ixe2x80x94I line and, IIxe2x80x94II line of FIG. 1 and FIGS. 3A and 3B showing section views of DRAM and section views of both IIIxe2x80x94III line and IVxe2x80x94IV line of FIG. 1, the constitution of the COB structure DRAM in which the bit contact hole and the node contact hole are made of self align contact hole are explained in a below description. An elements forming area is shown in hatching in FIG. 1, however, the drawing of a capacity insulation film constituting a capacitor and a cell plate electrode are omitted in FIGS. 1, 2A, 2B, 3A and 3B.
On a surface of a P type silicon substrate 301, T formed element forming areas are disposed regularly, a gate oxide film 303 with about 10 nm thickness is provided on the surface of 301. On a surface of element separation areas surrounding these element forming areas of the P type silicon substrate 301, a field oxide film 302 with for example LOCOS type about 300 nm thickness is provided. On the surface of the field oxide film 302 and the gate oxide film 303, a gate electrode 304 also served as a word line is provided in a certain direction in parallel. A line width and an interval of these gate electrodes 304 are for example about 0.4 xcexcm respectively, these gate electrodes 304 are constituted of a tungsten polycide film laminated an about 150 nm thickness tungsten silicide film to an about 100 nm thickness N type polycrystal silicon film (not shown in Figs.). On the surface of the P type silicon substrate 301 of the respective element forming areas, the gate electrode 304, one of N type source drain area 305 self matching to the field oxide film 302 and two N type source drain areas 306 are provided. The minimum line width and the minimum interval of the N type source drain area 305 and 306 are respectively about 0.4 xcexcm.
The surface of the P type silicon substrate 301 including the gate electrode 304, the field oxide film 302 and the gate oxide film 303 is covered with an insulation film between layers 310a made of a silicon oxide type insulation film. The surface of the insulation film between layers 310a is flattened and the film thickness of the insulation film between layers 310a from the surface of the P type silicon substrate 301 is about 500 nm. The upper surface of the insulation film between layers 310a and the bottom face of the insulation film between layers 310a covering directly the gate electrode 304 are constituted of at least a silicon oxide film.
At the insulation film between layers 310a, a bit contact hole 311 reaching the N type source drain area 305 penetrating the insulation film between layers 310a and the gate oxide film 303 from the surface of this insulation film between layers 310a is provided. The bit contact hole 311 is formed in self matching for the gate electrode 304 and penetrates the insulation film between layers 310a of the vacant part of the gate electrode 304. At the upper surface of the insulation film between layers 310a, an upper end bore of the bit contact hole 311 is about 0.5 xcexcm but the minimum bore of the bit contact hole 311 being at the lower part than the upper face of the gate electrode 304 is the same as an interval of the gate electrode 304 and is about 0.4 xcexcm, this minimum bore is a bore of an orthogonal direction of the gate electrode 304. The upper face and a part of a side face of the gate electrode 304 are exposed by the bit contact hole 311. The side face of the bit contact hole 311 is covered directly with a silicon oxide film spacer 312 of about 100 nm thickness except a part of the side face of the exposed gate electrode 304.
On the surface of the insulation film between layers 310a, a bit line 317 connecting to the N type source drain area 305 via the bit contact hole 311 is provided in parallel in an orthogonal direction of the gate electrode 304. The bit line 317 is the same as the gate electrode 304, is constituted of the tungsten polycide film laminated a tungsten silicide film 337 with about 150 nm thickness to an N type polycrystal silicon film 336 with about 100 nm thickness. A wiring pitch of the bit line 317 is about 0.8 xcexcm, a line width and an interval of the bit line 317 at the part of the bit contact hole 311 are about 0.5 xcexcm and 0.3 xcexcm, the line width and the interval of the bit line 317 except the part of the bit contact hole 311 is about 0.4 xcexcm. The surface of the insulation film between layers including these bit line 317 is covered with an insulation film between layers 320a constituting of a silicon oxide type insulation film. An upper face of the insulation film between layers 320a is also flattened and a thickness of the insulation film between layers 320a from the surface of the insulation film between layers 310a is about 350 nm. The upper face of the insulation film between layers 320a and the bottom face of the insulation film between layers 320a covering directly the bit line 317 are at least formed by the silicon oxide film (FIGS. 1, 2A and 2B).
In the insulation film between layers 320a, a node contact hole 321 reaching an N type source drain area 306 penetrating these insulation film between layers 320a, 310a and the gate oxide film 303 from this surface is provided. A node contact hole 321 is formed in self matching for the bit line 317 and penetrates the insulation film between layers 320a of the vacant part of the bit line 317, further is formed in self matching for the gate electrode 304 and penetrates the insulation film between layers 310a of the vacant part of the gate electrode 304. At the upper face of the insulation film between layers 320a, a bore of the node contact hole 321 is about 0.5 xcexcm and the minimum bore of the node contact hole 321 from the upper face of the bit line 317 to the upper face of the gate electrode 304 is about 0.4 xcexcm, a bore of the node contact hole 321 at the lower part than the upper face of the gate electrode 304 is about 0.4 xcexcm. By these node contact holes 321, the upper face and a part of the side of the bit line 317 and the upper face and a part of the side of the gate electrode 304 are exposed. A side of the node contact hole 321 except the exposed bit line 317 and a part of the side of the gate electrode 304 is covered directly with the silicon oxide film spacer 322 with about 100 nm thickness.
On the surface of the insulation film between layers 320a, a storage node electrode 327 connecting to the N type source drain area 306 via the node contact hole 321 is provided. The storage node electrode 327 is constituted of an N type polycrystal silicon film with about 700 nm thickness. A long length direction of the storage node electrode 327 is parallel with the bit line 317 and a length, a width and an interval of the storage node electrode 327 are about 1.3 xcexcm, 0.5 xcexcm and 0.3 xcexcm respectively, pitches of the storage node electrode 327 in a parallel direction of the bit line 317 and the gate electrode 304 are about 1.6 xcexcm and 0.8 xcexcm respectively (FIGS. 1, 3A and 3B).
Referring to FIGS. 1, 2A, 2B, 3A and 3B and FIGS. 4A, 4B and 4C showing section views of IIIxe2x80x94III line of FIG. 1 and FIGS. 5A, 5B and 5C showing section views of IVxe2x80x94IV line of FIG. 1, an outline of a manufacturing method of DRAM is stated below. The minimum processing dimension is about 0.3 xcexcm, an alignment margin in the photo lithography is about 0.05 xcexcm.
First, in an element separation area on a surface of the P type silicon substrate 301, for example a field oxide film 302 with about 300 nm thickness is formed by selective oxidation and in an element forming area on a surface of the P type silicon substrate 301, a gate oxide film 303 with about 10 nm thickness is formed by heat oxidation. On the whole surface, an N type polycrystal silicon film with about 100 nm thickness and a tungsten silicide film with about 150 nm thickness are formed in order, these tungsten silicide film and N type polycrystal silicon film are patterned by an anisotropic etching in order and a gate electrode 304 is formed. By an ion injection of arsenic As etc., using as a mask the gate electrode 304 and the field oxide film 302, in an element forming area of the surface of the P type silicon substrate 301 a source drain area 305 and 306 are formed. For example, a HTO film by the high temperature vapor phase grown method and a BPSG film used TEOS as a main gas material are formed on the whole surface, the BPSG film is reflowed by about 800xc2x0 C. heat treatment, further, after a surface of the BPSG film flattened by a chemical mechanical polishing, a silicon oxide film with about 100 nm thickness is formed on the whole surface and a first insulation film between layers with about 520 nm thickness which corresponds to a height from the surface of the P type silicon substrate 301 is formed.
Next, by a high selectivity anisotropic etching for the polycrystal silicon film and tungsten suicide film and so on using a photo resist pattern to the mask, the first insulation film between layers and the gate oxide film 303 are etched and a bit contact hole 311 reaching from the upper surface of the first insulation film between layers to the N type source drain area 305 is formed. At this time, a slit width of the upper surface of the gate electrode 304 disposed by the bit contact hole 311 is about 50 nm disregarding the alignment margin. By LPCVD, a silicon oxide film with about 100 nm thickness is formed on the whole surface. This silicon oxide film is etch backed by the anisotropic etching, a silicon oxide film spacer 312 covered the side of the bit contact hole 311 is formed. Together with this, the first insulation film between layers is also etch backed and becomes the insulation film between layers 310a with about 500 nm thickness. At the bottom face of the bit contact hole 311, the minimum width of the N type source drain area 305 exposed and not covered by the silicon oxide film spacer 312 is about 200 nm. At the near part to the upper surface of the side of the gate electrode 304 exposed by the bit contact hole 311, disregarding the alignment margin, the thickness of the silicon oxide film spacer 312 is about 50 nm at that part (FIGS. 1, 2A and 2B).
In the next process, an N type polycrystal silicon film 336 with about 100 nm thickness and a tungsten silicide film 337 with about 150 nm thickness are formed on the whole surface. By the anisotropic etching, a tungsten silicide film 337 and an N type polycrystal silicon film 336 are formed in order, a bit line 317 connecting to the N type source drain area 305 via the bit contact hole 311 is formed. To avoid occurrence of issues of the insulation separation between the bit line 317 and the gate electrode 304 and parasitic capacity between them, a thickness of the silicon oxide film spacer 312 is about 30 nm enough, even in case of the silicon oxide film spacer is constituted of the vapor phase grown film (FIGS. 1, 2A and 2B).
Then, by the same method forming the first insulation film between layers, an insulation film between layers 320 with about 370 nm thickness is formed (FIGS. 4A and SA). By the same method forming the bit contact hole 311, an insulation film between layers 320, 310a and the gate oxide film 303 are etched by the anisotropic etching, a node contact hole 321 reaching the N type source drain area 306 from an upper surface of the insulation film between layers 320 is formed. At this time, the slit widths of the upper surface of the gate electrode 304 and the bit line 317 exposed by the node contact hole 321 are about 50 nm respectively, disregarding the alignment margin. By LPCVD, a silicon oxide film 342 with about 100 nm thickness on the whole surface is formed (FIGS. 4B and 5B).
The silicon oxide film 342 is etch backed by the anisotropic etching, a silicon oxide film spacer 322 covering the side of the node contact hole 321 is formed. With this, the insulation film between layers 320 is also etch backed and becomes an insulation film between layers 320a with about 500 nm thickness. At the near part to the upper surface of the side of the gate electrode 304 and the bit line 317 exposed by the node contact hole 321, disregarding the alignment margin, the width of the silicon oxide film spacer 312 is about 50 nm at that part (FIGS. 1, 4C and 5C).
After this, by LPCVD, a silicon film made of an N type amorphous or polycrystal at the process of film forming is formed. The thickness of this silicon film is about 700 nm. This silicon film is patterned by the anisotropic etching and a storage node electrode 327 being finally an N type polycrystal silicon film implemented heat treatment if needed is formed (FIGS. 1, 2A, 2B, 3A and 3B).
As shown in FIGS. 1 to 5C, on condition that the bit contact hole and the node contact hole of DRAM are the self align contact holes, step parts formed by the exposure of the wiring layer of middle layer at the side of the respective contact holes are formed, of necessity. At the bit contact hole, one part of the N type source drain areas becomes a lower wiring layer, the gate electrode becomes a middle wiring layer and the bit line becomes an upper wiring layer. At the node contact hole, the other part of the N type source drain areas becomes a lower wiring layer, the bit line and the gate electrode become middle wiring layers and the storage node electrode becomes an upper wiring layer.
A surface shape of the silicon oxide film formed on the whole surface having a shape covering the side and bottom surfaces of the self align contact hole is somewhat lessened the shape of step parts at the middle wiring layer but reflects the shape of these step parts. A silicon oxide film spacer covering the side of the self align contact hole is formed by the etch back of the silicon oxide film having the surface somewhat lessened the shape of the step parts, therefore at least at the near part to the upper surface of the side of the step part of the middle wiring layer exposed by the self align contact hole, thinning of the thickness of the silicon oxide film spacer partly can not be avoided. The thickness of the silicon oxide film spacer at the partly thinned part is decided by the upper end bore of the self align contact hole, the interval of the middle wiring layer and the thickness of the silicon oxide film spacer formed on the whole surface becoming this silicon oxide film spacer and the alignment margin at the photo lithography, and not decided only by the above mentioned thickness of the silicon oxide film. A small change of the thickness of the silicon oxide film spacer in the above mentioned part largely depends on this alignment margin. Therefore, the decreasing of the insulation characteristics including leak and short between the upper wiring layer/lower wiring layer connecting to the upper wiring layer and the middle wiring layer is liable to occur.
For example, as mentioned in the Japanese Patent Laid-Open Ser. No. 6-177265, by covering the upper surface of the gate electrode with a silicon nitride film cap, forming a silicon oxide film spacer at the side of the gate electrode, furthermore forming a silicon nitride film spacer which covers the silicon oxide film spacer and then forming a self align contact hole for the gate electrode, only the point lessening the lowering of the insulation characteristics is solved. However, the part between the upper wiring layer/the diffusion layer being the lower wiring layer and the gate electrode becomes a NMOS type nonvolatile memory at the constitution of said Japanese Patent, an electric charge is stored in the silicon nitride film spacer and a new electric characteristics issue occurs. In case of the constitution of said Japanese Patent, the silicon nitride film cap and the silicon nitride film spacer must be formed in the whole wiring layers being the middle wiring layers. Therefore, a complicated manufacturing process for forming the middle wiring layer is required in this kind of the constitution of the semiconductor device.
It is therefore an object of the present invention to resolve all the problems mentioned, and to provide a semiconductor device capable of restraining the deterioration of the insulation characteristics between the upper wiring layer/the lower wiring layer connecting to this upper wiring layer and the middle wiring layer via the self align contact hole, without storing an electric charge in the insulation film spacer formed at the side of the self align contact hole. Moreover, it is another object of the present invention to provide a manufacturing method of said semiconductor device and provide a manufacturing method which does not require a complicated manufacturing process forming the middle wiring layer.
The present invention, there is provided a lower wiring layer formed at or on a surface of a semiconductor substrate, an insulation film covering the surface of this semiconductor substrate, a middle wiring layer formed on the surface of this insulation film, an insulation film between layers covering these middle wiring layers and an upper wiring layer formed on the surface of the insulation film between layers. Said upper wiring layer reaches to said lower wiring layer penetrating said insulation film between layers and said insulation film and connects to this lower wiring layer via a self align contact hole in self matching for said middle wiring layer. On the side of said self align contact hole, an insulation film spacer made of a BPSG film or a PSG film reflowed by heat is at least formed.
According to a first aspect of the present invention, there is provided a lower wiring layer formed at or on a surface of a semiconductor substrate, an insulation film covering the surface of this semiconductor substrate, a middle wiring layer formed on the surface of this insulation film, an insulation film between layers covering these middle wiring layers and an upper wiring layer formed on the surface of the insulation film between layers. Said upper wiring layer reaches to said lower wiring layer penetrating said insulation film between layers and said insulation film and connects to this lower wiring layer via a self align contact hole self matching for said middle wiring layer. The side of said self align contact hole is directly covered with a first insulation film spacer made of a silicon oxide film, moreover this first insulation film spacer is covered with a second insulation film spacer made of a BPSG film or a PSG film reflowed by heat. It is desirable that a polycrystal silicon film spacer covering said second insulation film spacer is provided and an upper end of said polycrystal silicon film spacer is positioned at lower place than an upper end of said self align contact hole.
According to a second aspect of the present invention, there is provided a lower wiring layer formed at or on a surface of a semiconductor substrate, an insulation film covering the surface of this semiconductor substrate, a middle wiring layer formed on the surface of this insulation film, an insulation film between layers covering these middle wiring layers and an upper wiring layer formed on the surface of the insulation film between layers. Said upper wiring layer reaches to said lower wiring layer penetrating said insulation film between layers and said insulation film and connects to this lower wiring layer via a self align contact hole in self matching for said middle wiring layer. On the surface of said middle and lower wiring layer exposed to said self align contact hole, a silicon oxide film by heat oxidation is formed selectively, on the side of said self align contact hole, an insulation film spacer made of a BPSG film or a PSG film reflowed by heat is formed and said insulation film spacer covers the surfaces of said middle and lower wiring layers exposed to said self align contact hole via said silicon oxide film. Moreover this silicon oxide film formed on the surface of said lower wiring layer is opened to the insulation film spacer in self matching. It is desirable that a polycrystal silicon film spacer covering said insulation film spacer is provided and an upper end of said polycrystal silicon film spacer is positioned at lower place than an upper end of said self align contact hole.
According to a third aspect of the present invention, there is provided a process forming a lower wiring layer at or on a surface of a semiconductor substrate, a process forming an insulation film covering the surface of said semiconductor substrate, a process forming a middle wiring layer on the surface of said insulation film and an insulation film between layers covering said middle wiring layer, a process forming a self align contact hole in self matching for said middle wiring layer which reaches to said lower wiring layer penetrating said insulation film between layers and said insulation film, a process forming in order a silicon oxide film and a BPSG film or a PSG film on the whole surface by LPCVD and reflowing said BPSG film or said PSG film by heat, a process forming a first insulation film spacer made of a silicon oxide film by an etch back said BPSG film or said PSG film and said silicon oxide film in order with an anisotropic etching and forming a second insulation film spacer made of the BPSG film or PSG film and a process forming an upper wiring layer connecting to said lower wiring layer via said self align contact hole on the surface of the insulation film between layers.
According to a fourth aspect of the present invention, there is provided a process forming a lower wiring layer at or on a surface of a semiconductor substrate, a process forming an insulation film covering the surface of said semiconductor substrate, a process forming a middle wiring layer on the surface of said insulation film and an insulation film between layers covering said middle wiring layer, a process forming a self align contact hole in self matching for said middle wiring layer which reaches to said lower wiring layer penetrating said insulation film between layers and said insulation film, a process forming a silicon oxide film and a BPSG film or a PSG film on the whole surface in order by LPCVD and reflowing said BPSG film or said PSG film by heat, a process forming a polycrystal silicon film spacer which upper end is positioned at a lower place than the upper end of said self align contact hole by forming a polycrystal silicon film on the whole surface by LPCVD and by an etch back said polycrystal film with a selective anisotropic etching for a silicon film, a process forming a second insulation film spacer made of the BPSG film or the PSG film and forming a first insulation film spacer made of the silicon oxide film by an etch back said BPSG film or said PSG film and said silicon oxide film in order by an anisotropic etching used said polycrystal silicon film spacer as a mask and a process forming an upper wiring layer connecting to said lower wiring layer via said self align contact hole on the surface of said insulation film between layers.
According to a fifth aspect of the present invention, there is provided a process forming a lower wiring layer at or on a surface of a semiconductor substrate, a process forming an insulation film covering the surface of said semiconductor substrate, a process forming a middle wiring layer on the surface of said insulation film and an insulation film between layers covering said middle wiring layer, a process forming a self align contact hole in self matching for said middle wiring layer which reaches to said lower wiring layer penetrating said insulation film between layers and said insulation film, a process transforming a silicon film to a silicon oxide film by high speed heat treatment in an oxygen ambience by selectively growing a silicon film of required thickness on the surface of said middle and lower wiring layers exposed by said self align contact hole, a process forming a BPSG film or a PSG film on the whole surface by LPCVD and reflowing said BPSG film or said PSG film by heat, a process forming an insulation film spacer made of the BPSG film or the PSG film by an etch back the BPSG film or PSG film by an anisotropic etching and a process forming an upper wiring layer connecting to said lower wiring layer via said self align contact hole on the surface of said insulation film between layers.
According to a sixth aspect of the present invention, there is provided a process forming a lower wiring layer at or on a surface of a semiconductor substrate, a process forming an insulation film covering the surface of said semiconductor substrate, a process forming a middle wiring layer on the surface of said insulation film and an insulation film between layers covering said middle wiring layer, a process forming a self align contact hole in self matching for said middle wiring layer which reaches to said lower wiring layer penetrating said insulation film between layers and said insulation film, a process transforming a silicon film to a silicon oxide film by high speed heat treatment in an oxygen ambience by selectively growing a silicon film of required thickness on the surface of said middle and lower wiring layers exposed by said self align contact hole, a process forming a BPSG film or a PSG film on the whole surface by LPCVD and reflowing said BPSG film or said PSG film by heat, a process forming a polycrystal silicon film on the whole surface by LPCVD and forming a polycrystal silicon film spacer which upper end is positioned at the lower place than an upper end of said self align contact hole by an etch back said polycrystal silicon film by a selective anisotropic etching for the silicon film, a process forming an insulation film spacer made of said BPSG film or said PSG film by an etch back the said BPSG film or said PSG film by an anisotropic etching using said polycrystal silicon film spacer as a mask and a process forming an upper wiring layer connecting to said lower wiring layer via said self align contact hole on the surface of said insulation film between layers.